1. Field of the Invention
The present invention relates to an integrated circuit for a semiconductor device. More specifically, the present invention relates to a method for forming an isolated trench in the integrated circuit of a semiconductor device.
2. Discussion of the Related Art
As the demand for high-performance, compact, highly integrated semiconductors has increased, technologies for isolating the individual circuits in the integrated semiconductor and reducing the gate line width of the Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have become increasingly important.
One method for isolating the individual devices within the semiconductor uses local oxidation of silicon (LOCOS) technology, wherein an oxide layer is used to separate the components, so that no electrical current is leaked from one component to another. Examples of LOCOS processes are Thin Oxide LOCOS (TOLOCOS) processes which use a very thin pad oxide layer of 50 Å thick or less to separate the components, Poly Buffered LOCUS (PBL) processes, Nitride Spacer LOCOS (NSLOCOS) processes which use a nitride layer as a spacer, Poly Spacer LOCOS (PSLOCUS) processes which use poly silicon, and Si Recessed LOCOS (SRLOCOS) processes wherein an oxide layer is grown after an etching process used to form a Si layer in a field region that is hundreds of Å thick.
Unfortunately, however, the LOCOS processes have many limitations. For example, the processes may generate “bird's beak” regions which reduce the effective size of the active region. Furthermore, difficulties in the processes due to varying topology effect the volume ratio of a field oxide layer, while difficulties controlling the electrical characteristics of devices due to thinning of field regions cause other problems. Because of these limitations, the number of processes required and cost of manufacturing the semiconductor device is increased.
Because of these limitations, another configuration, referred to as Shallow Trench Isolation (STI) is widely used for the isolating the components in integrated circuit devices of 0.25 μm or less. Such STI isolations are suitable for achieving high integration in integrated circuit semiconductor devices since they have excellent isolation characteristics and are compact in size.
An STI isolation is generally formed by sequentially forming a pad oxide layer and a pad nitride layer on a silicon substrate. Then, an exposed area of the silicon substrate is etched to form a trench. Selected parts of the pad oxide layer and the pad nitride layer are etched so as to expose top corners of the trench. Then, a dry etch process is performed in order to round the corners of the trench and a thermal oxidation process is then performed to form an oxide layer on the surface of the trench. Then, the oxide layer is deposited so as to fill the interior of the trench. Then, a Chemical Mechanical Polishing (CMP) process is performed to complete the trench isolation process.
However, one difficulty that arises during the procedure of forming the STI isolations is that the corners of the active areas formed between the field and isolation areas have angles of 90 degrees or more, meaning that the strength of electric field applied to the gate oxide layer is significantly raised at the corner areas. This degrades the electrical characteristics of the device, and may cause leakage current and dielectric breakdown. Additionally, hump phenomena may occur as the channel regions of the corner areas are more rapidly inversed causing the bulk voltage to increase beyond the threshold voltage characteristics of most transistors. Thus, the corner areas degrade the electrical characteristics and reliability of the semiconductor integrated circuit devices. In order to eliminate the corner areas, various attempts have been made to round the corner areas of trenches.
FIG. 1 is a sectional view illustrating a conventional process for forming a rounded corner portion of a trench isolation. First, an oxide layer 12 and a nitride layer 14 are coated on a semiconductor substrate 10. Then a trench mask 16 is then formed into a pattern. The oxide layer 12 and the nitride layer 14 are then dry etched using the trench mask 16 as a mask. When the silicon substrate 10 is dry etched to form a trench 15, a polymer is formed on sidewalls of the trench from etching the oxide and nitride layers 12 and 14 using a gas such as Hbr. Once the trench has been formed, any polymer formed on the sidewalls of the nitride layer 14 during the etching process is removed, using, for example, a natural processes, so as to expose an area of the silicon below the sidewall polymer. The newly exposed silicon area is etched at a later time, resulting in a rounded portion 17 along top corners of the trench 15.
One problem of using the conventional method described above, however, is that the sidewall polymer is a byproduct of the plasma dry etching, meaning that the shape of the rounded portion 17 varies depending on the density of the etching pattern. Thus, in high integrated semiconductor devices of 0.13 μm or less, the shape of the rounded portion 17 may vary significantly depending on the specific etching pattern density. Because of this variation, the difference between the electrical characteristics, such as the hump phenomena and saturation current of the isolated areas, in the narrow and wide areas of the pattern may be very large.
In the conventional technology shown in FIG. 1, it is also difficult to perform control based on Micro-Loading Effects (MLE) in order to manage the fabrication processes since an excessive amount of polymer is formed during the dry etching process.
Another process used to round the corner of the trench isolation is a rounding oxidation method. In this method, a thermal oxide layer is formed after the trench 15 is formed and the rounded corner portion is formed by removing a portion the thermal oxide layer. Unfortunately, however, this method also results in variations since relatively large rounded corners are formed in narrow active areas and relatively small rounded corners are formed in wide active areas. This problem is more serious when manufacturing highly integrated semiconductor circuit devices of 0.13 μm or less.